Stack semiconductor package including an interposer chip having an imposed diode or capacitor

ABSTRACT

A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

PRIORITY STATEMENT

This U.S. non-provisional application claims the benefit of priority ofKorean Patent Application No. 10-2006-0091143, filed on Sep. 20, 2006 inthe Korean Intellectual Property Office (KIPO), the disclosure of whichis incorporated herein in its entirety by reference.

BACKGROUND

1. Field

Example embodiments relate to a semiconductor package, a method ofmanufacturing the semiconductor package, and method of using thesemiconductor package.

2. Description of the Related Art

The electronics market is currently growing in the area of mobileelectronics products. Electronic components, for example, semiconductordevices, that may be installed in mobile electronics products should belighter and smaller-sized. Accordingly, semiconductor devices have beendeveloped that may be reduced in size; that may include severalindividual semiconductor devices in one semiconductor chip, which iscalled a system on chip (SOC); and/or that may include a plurality ofsemiconductor chips packaged in one semiconductor package, which iscalled a system in package (SIP).

According to SIP technology, a plurality of semiconductor chips ismounted on a lead frame or a substrate. The semiconductor chips aremounted horizontally or vertically with respect to a semiconductorpackage. SIP technology shares a similar concept with conventionalmulti-chip module (MCM) technology. The difference is that whereasconventional MCM technology includes mounting semiconductor chips in ahorizontal direction, SIP technology includes forming a semiconductorstack package in which semiconductor chips are stacked vertically.

Meanwhile, if a semiconductor stack package is formed using conventionalsemiconductor chips, the positions of the pads in the semiconductorchips will be the same regardless of the type of semiconductor stackpackage. Thus, a number of wiring layers in a wiring substrate, forexample, in a PCB, is increased. In order to reduce the number of wiringlayers in the PCB, an interposer chip may be stacked between thesemiconductor chips.

However, a conventional interposer chip includes only an input/output(I/O) bonding pad for connecting upper and lower semiconductor chips.Thus, if the bonding pad of the interposer chip is wire-bonded, forexample, with gold, it may not be detected whether the wire-bonding wassuccessful.

For example, non-stick defects may occur in which a wire is not properlybonded to a bonding pad of an interposer chip. If a non-stick defectoccurs, it will be determined that all of the semiconductor chips aredefective, rather than the discovering the defective wire-bond.Accordingly, the yield of the semiconductor stack package will bedecreased. Also, if wire-bonding defects in the bonding pad of theinterposer chip are not detected, the semiconductor stack package mayproceed to a subsequent process, thus increasing the burden inperforming further testing, which in turn may increase the cost.

SUMMARY

Example embodiments may provide a stacked semiconductor packageincluding an interposer chip that enables wire-bond monitoring.

Example embodiments may provide a method of manufacturing a stackedsemiconductor package which enables wire-bond monitoring of aninterposer chip.

In an example embodiment, a stacked semiconductor package may include awiring substrate. A first semiconductor chip may be disposed on thewiring substrate and wire-bonded to the wiring substrate. An interposerchip may be disposed on the first semiconductor chip and wire-bonded tothe wiring substrate. The interposer chip may include a circuit elementand a bonding pad being electrically connected. A second semiconductorchip may be disposed on the interposer chip and wire-bonded to theinterposer chip, the second semiconductor chip being electricallyconnected to the wiring substrate through the interposer chip.

According to an example embodiment, the circuit element may be connectedto a grounding pad or a grounding line.

According to an example embodiment, the circuit element may be a diode.

According to an example embodiment, the circuit element may be acapacitor.

In an example embodiment, a method of manufacturing a stackedsemiconductor package may include disposing a first semiconductor chipon a wiring substrate; wire-bonding the first semiconductor chip to thewiring substrate; disposing an interposer chip on the firstsemiconductor chip, the interposer chip including a circuit element anda bonding pad being electrically connected; wire-bonding a bonding padof the interposer chip and the wiring substrate; disposing a secondsemiconductor chip on the interposer chip; and wire-bonding the secondsemiconductor chip to the bonding pad of the interposer chip toelectrically connect the second semiconductor chip to the wiringsubstrate.

According to an example embodiment, the method may include connectingthe circuit element to a grounding pad or a grounding line.

According to an example embodiment, the circuit element may be a diode.

According to an example embodiment, the circuit element may be acapacitor.

In an example embodiment, a method of monitoring a wire-bond of astacked semiconductor package, the method may include applying a currentto the bonding pad of the interposer chip; measuring one of a current orvoltage of the circuit element; and comparing the measured current orvoltage of the circuit element to a reference current or voltage,respectively

According to an example embodiment, the circuit element may be a diode,and applying the current may include applying a direct current to thebonding pad of the interposer chip.

According to an example embodiment, the circuit element may be acapacitor, and applying the current may include applying an alternatingcurrent to the bonding pad of the interposer chip.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be described with reference to the accompanyingdrawings.

FIG. 1 is a cross-sectional view of a stacked semiconductor packageaccording to an example embodiment.

FIG. 2 is a perspective view of the stacked semiconductor package ofFIG. 1.

FIGS. 3 and 4 are schematic views of an interposer chip according to anexample embodiment.

FIG. 5 is a cross-sectional view of an interposer chip according to anexample embodiment.

FIG. 6 is a cross-sectional view of a conventional interposer chip.

FIGS. 7 and 8 are schematic views illustrating monitoring ofwire-bonding of an interposer chip of a stacked semiconductor package.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully with reference tothe accompanying drawings. Example embodiments may, however, be embodiedin many different forms and should not be construed as being limited tothe example embodiments set forth herein. Rather, these exampleembodiments are provided so that this disclosure will be thorough, andwill fully convey the concept of the invention to those skilled in theart. In the drawings, the thicknesses of layers and regions areexaggerated for clarity.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes” and/or “including,” when usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the scope of the example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or a relationship between a feature and anotherelement or feature as illustrated in the figures. It will be understoodthat the spatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the Figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, for example, the term “below” can encompass both anorientation which is above as well as below. The device may be otherwiseoriented (rotated 90 degrees or viewed or referenced at otherorientations) and the spatially relative descriptors used herein shouldbe interpreted accordingly.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures). As such, variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, may be expected. Thus,example embodiments should not be construed as limited to the particularshapes of regions illustrated herein but may include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may have rounded or curvedfeatures and/or a gradient (e.g., of implant concentration) at its edgesrather than an abrupt change from an implanted region to a non-implantedregion. Likewise, a buried region formed by implantation may result insome implantation in the region between the buried region and thesurface through which the implantation may take place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes donot necessarily illustrate the actual shape of a region of a device anddo not limit the scope.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms used herein should be interpretedas having a meaning that is consistent with their meaning in the contextof this specification and the relevant art and will not be interpretedin an idealized or overly formal sense unless expressly so definedherein.

According to an example embodiment, a stacked semiconductor package mayinclude an interposer chip that enables monitoring of wire-bonding. Thestacked semiconductor package may include a plurality of semiconductorchips on a wiring substrate, for example, three or more semiconductorchips. The stacked semiconductor package may include an interposer chip.The stacked semiconductor package may be applied regardless of the stackposition, the size of the interposer chip, the method of stacking theinterposer chip, the form of the package, and/or the size or form of thesemiconductor chip. An interposer chip may be applied between thesemiconductor chips of the stacked semiconductor package regardless ofwhether the semiconductor chips are stacked vertically, horizontally, ora vertically stacked semiconductor chip stack is arranged in parallel.

FIG. 1 is a cross-sectional view of a stacked semiconductor packageaccording to an example embodiment. FIG. 2 is a perspective view of thestacked semiconductor package of FIG. 1.

A stacked semiconductor package may include a wiring substrate 10. Lead14 may be formed on an upper surface of the wiring substrate 10.Conductive bumps, for example, solder balls 12, may be formed on a lowersurface of the wiring substrate 10.

A first semiconductor chip 18 may be disposed on the wiring substrate10. A first adhesion layer 16 may be interposed between the wiringsubstrate 10 and the first semiconductor chip 18. A first bonding wire20 may be wire-bonded to a wiring pad (not shown) of the firstsemiconductor chip 18 and the leads 14 of the wiring substrate 10.

An interposer chip 24 may be disposed on the first semiconductor chip18. A second adhesion layer 22 may be interposed between the firstsemiconductor chip 18 and the interposer chip 24. A bonding pad (notshown) of the interposer chip 24 and the leads 14 of the wiringsubstrate 10 are wire-bonded with a second bonding wire 26.

If a pad (or alternatively, a pin, ball, or lead) for signal, power,and/or grounding of a stack package is integrated in the interposer chip24, the interposer chip 24 may reduce the wiring layer in the wiringsubstrate 10. If each semiconductor chip is wire-bonded, the interposermay reduce the length of the wiring. A circuit element (not shown), forexample, a diode or a capacitor, may be connected to a bonding pad (notshown) of the interposer chip 24 to produce a polarity and a currentflow if the interposer chip 24 is wire-bonded to a bonding pad (notshown). Thus, the circuit element may enable wire-bond monitoring, whichwill be described below in more detail.

A second semiconductor chip 30 may be disposed on the interposer chip24. A third adhesion layer 28 may be interposed between the interposerchip 24 and the second semiconductor chip 30. A bonding pad (not shown)of the second semiconductor chip 30 and a bonding pad (not shown) of theinterposer chip 24 may be wire-bonded with a third bonding wire 32. Thesecond semiconductor chip 30 may be electrically connected to the wiringsubstrate 10 through the interposer chip 24. A spacer 36 may be disposedon the second semiconductor chip 30. A fourth adhesion layer 34 may beinterposed between the second semiconductor chip 30 and the spacer 36.The spacer 36 may facilitate wire-bond a third semiconductor chip 40, tobe subsequently attached.

A third semiconductor chip 40 may be disposed on the spacer 36. A fifthadhesion layer 38 may be interposed between the spacer 36 and the thirdsemiconductor chip 40. A fourth bonding wire 42 may be wire-bonded to abonding pad (not shown) of the third semiconductor chip 40 and a bondingpad (not shown) of the interposer chip 24. The third semiconductor chip40 may be electrically connected to the wiring substrate 10 through theinterposer chip 24. As described above, the interposer chip 24 may be anintermediate to electrically connect the second and third semiconductorchips 30 and 40 and the wiring substrate 10. An encapsulant 44 may beformed to protect and cover the first, second, and third semiconductorchips 18, 30, 40, the interposer chip 24, and the spacer 36. Forexample, the encapsulant 44 may be an epoxy resin.

According to an example embodiment, as shown in FIG. 1, the secondsemiconductor chip 30 and the third semiconductor chip 40, which arestacked vertically on the interposer chip 24, may be electricallyconnected to the wiring substrate 10. In another example embodiment, thesecond semiconductor chip 30 and the third semiconductor chip 40, whichare stacked horizontally, may be electrically connected to the wiringsubstrate 10.

Referring to FIG. 1, a method of manufacturing a stacked semiconductorpackage, according to an example embodiment, may include disposing afirst semiconductor chip 18 on a wiring substrate 10. The firstsemiconductor chip 18 may be wire-bonded to the wiring substrate 10using a first bonding wire 20. An interposer chip 24 may be disposed onthe first semiconductor chip 18. The interposer chip 24 may include acircuit element that may have a polarity and a current flow. A bondingpad of the interposer chip 24 may be wire-bonded to the wiring substrate10 using a second bonding wire 26.

A second semiconductor chip 30 may be disposed on the interposer chip24. The second semiconductor chip 30 may be wire-bonded to a bonding padof the interposer chip 24 using the third bonding wire 32 toelectrically connect to the wiring substrate 10. A spacer 36 may bedisposed on the second semiconductor chip 30. A third semiconductor chip40 may be disposed on the spacer 36. The third semiconductor chip 40 maybe wire-bonded to a bonding pad of the interposer chip 24 using a fourthbonding wire 42 to electrically connect the third semiconductor chip 40to the wiring substrate 10. An encapsulant 44 may be formed to cover thefirst, second, and third semiconductor chips 18, 30 and 40, theinterposer chip 24, and the spacer 36. For example, the encapsulant 44may be an epoxy resin.

Wire monitoring may be performed on the second, third, and fourthbonding wires 26, 42 and 42 that are wire-bonded to a bonding pad of theinterposer chip 24.

In the example embodiment described above, with reference to FIG. 1, themethod may include disposing each of the first, second, and thirdsemiconductor chips 18, 30, and 40 and the interposer chip 24, and thenwire-bonding each element. However, in another example embodiment, amethod may include directly attaching the first, second, and thirdsemiconductor chips 18, 30, and 40, the interposer chip 24, and thespacer 36 to the wiring substrate 10, depending on the size of eachsemiconductor chip and/or the interposer chip 24, and wire-bonded at thesame time.

FIGS. 3 and 4 are schematic views of an interposer chip according to anexample embodiment. FIG. 5 is a cross-sectional view of an interposerchip according to an example embodiment. FIG. 6 is a cross-sectionalview of a conventional interposer chip.

Referring to FIGS. 3 to 5, an interposer chip 24 may include a circuitelement, for example, a diode 54 or a capacitor 56. A bonding pad 50 maybe connected to the circuit element. The circuit element may have apolarity and may cause a current to flow through the silicon substrate80. The circuit element may be connected to a grounding pad 52 orgrounding line.

Referring to FIGS. 3 and 5, the bonding pad 50 may be connected to adiode 54 formed in the silicon substrate 80. The diode 54 may be an N-Ptype diode including a P well 82 (P type impurities) and an N+ well (Ntype impurities). The N-P type diode 54 may be connected to a groundingpad 52 or a grounding line. The N-P type diode 54 is may be connected tothe silicon substrate 80 below the bonding pad 50.

Referring to FIG. 5, a P well 82 may be formed in the silicon substrate80. An N+ well 84 may be formed in the P well 82, such that only the Pwell 82 may be grounded to the silicon substrate 80. The N+ well and Pwell may be formed in a portion of the substrate 80 below where thebonding pad 50 is to be formed. The P well 82 may extend below where thegrounding pad 52 is to be formed.

An interlayer insulating layer 88 may be formed on the surface of thesilicon substrate 80. The bonding pad 50 and the grounding pad 52 may beformed on the interlayer insulating layer 88. Contact plugs 86 may beformed in the interlayer insulating layer 88 to connect the N+ well 84to the bonding pad 50 and the P well 82 to the grounding pad 52.

A bonding wire may be wire-bonded to the bonding pad 50, and a voltagemay be applied to the bonding pad 50 to perform wire-bond monitoring.

If the diode 54 is an N-P type diode, as shown in FIG. 5, a greatervoltage may be applied to the grounding pad 52 than to the bonding pad50, producing a current that flows from the grounding pad 52 to thebonding pad 50, thereby enabling wire-bond monitoring.

If the diode 54 is a P-N type diode (not shown), a greater voltage maybe applied to the bonding pad 50 than to the grounding pad 52, producinga current flows from the bonding pad 50 to the grounding pad 52, therebyenabling wire-bond monitoring.

Referring to FIG. 4, the bonding pad 50 may be connected to a capacitor56 formed in the silicon substrate 80. The capacitor 56 may be connectedto a grounding pad 52 or a grounding line. Accordingly, if a bondingwire is wire-bonded to the bonding pad 50, there may be a polaritybetween the grounding pad 52 and the bonding pad 50 due to the capacitor56, and current may flow through the capacitor 56, thereby enablingwire-bond monitoring.

In contrast, in a conventional interposer chip 24 a illustrated in FIG.6, an insulating layer 60 and a metal layer 58 may be sequentiallyformed on a silicon substrate 90. A bonding pad 50 a may be disposed onthe upper layer. For example, the boding pad 50 a may be formed of thesame material as the metal layer 58. The insulating layer 60 may beformed to a thickness of about 9000 Å, and the metal layer 58 and/or thebonding pad 50 a may be formed to a thickness of 5700 Å.

Accordingly, because a conventional interposer chip 24 a includes abonding pad 50 a which does not have a polarity and is not grounded,current may not flow through if a bonding wire is wire-bonded to thebonding pad 50 a. Thus, wire-bond monitoring may not be possible.

FIGS. 7 and 8 are schematic views illustrating a wire-bond monitoringmethod for an interposer chip of a stacked semiconductor package,according to an example embodiment.

Referring to FIGS. 7 and 8, a wire-bonding apparatus may include awire-bond monitoring system (WBMS). For convenience, the wire-bondmonitoring of the bonding pad 50 will be described with reference to aninterposer chip 24 disposed on a heater block 70. In FIG. 7, a diode 54may be connected to the bonding pad 50 of an interposer chip 24,according to an example embodiment as shown in FIGS. 3 and 5. In FIG. 8,a capacitor 56 may be connected to the bonding pad 50 of the interposerchip 24, according to an example embodiment as shown in FIG. 6.

A wire 77 that is drawn out from a wire spool 76 of the wire-bondingapparatus illustrated in FIGS. 7 and 8 may be inserted into a capillary72 through a wire clamp 74. The wire 77 inserted into the capillary 72may be wire-bonded to the bonding pad 50 of the interposer chip 24, forexample, by ball bonding. A current, e.g., either a direct oralternating current, may be applied to the wire 77 through the wireclamp 74 in the wire-bond monitoring system. The current or voltageflowing through the circuit element, e.g., the diode 54 or the capacitor56, may be checked to determine whether the wire-bond is bonded properlyto the bonding pad 50. Accordingly, non-stick defects, e.g., defectivebonding of the bonding pad 50 and a bonding wire, may be detected.

Referring to FIG. 7, a direct current may be applied to the wire 77through the wire clamp 74 in the wire-bond monitoring system 78 asdescribed above. If a direct current is applied to the wire 77, and thedirect current applies a greater voltage to the grounding pad 52 than tothe bonding pad 50, current may flow from the grounding pad 52 to thebonding pad 50. The current may be fed back to the wire 77 and the clamp74 to check the current or the voltage in the wire-bond monitoringsystem 78 to monitor the wire-bond.

During the checking of the current (or the voltage), a reference current(or a reference voltage) stored in the wire-bond monitoring system 78and the checked current (or voltage) may be compared. Alternatively, thechecked currents (or voltages) may be compared using a plurality ofbonding pads of the interposer chip 24 in the wire-bond monitoringsystem 78. Thus, it may be determined whether the wire-bond is bondedproperly to the bonding pad 50.

If the diode 54 is a P-N type diode, and a greater voltage is applied tothe bonding pad 50 than to the grounding pad 52 by the direct current,current may flow from the bonding pad 50 to the grounding pad 52. Thecurrent may be checked in the wire-bond monitoring system 78 using aconnection line 73, represented as a dotted line in FIG. 7, to determinewhether the wire-bonding is properly bonded to the bonding pad 50.

For example, if wire-bond monitoring is performed by applying directcurrent to the bonding pad 50 of the interposer chip 24, the resistanceand the current of the diode 54 may be a less than about 8 Mohm and 2μA, respectively.

Referring to FIG. 8, an alternating current may be applied to the wire77 through the wire clamp 74 in the wire-bond monitoring system 78. Ifan alternating current is applied to the wire 77, there may be apolarity between the bonding pad 50 and the grounding pad 52, betweenwhich current may flow. The current or the voltage fed back to the wireclamp 74 in the wire-bond monitoring system 78 may be checked to monitorthe wire-bond. The checking method may be performed as described beforewith reference to FIG. 7.

Wire-bond monitoring may be performed by checking current or voltage inthe wire-bond monitoring system 78 through a connection line 73connected to the grounding pad 52. For example, if the wire-bondmonitoring is performed by applying an alternating current to thebonding pad 50 of the interposer chip 24, the capacitance of thecapacitor 56 may be about 15 to 20 pF.

According to example embodiments, wire-bond monitoring may be performedin a stacked semiconductor package by connecting a circuit element, forexample, a diode or a capacitor, that may have a polarity and may causecurrent to flow to a bonding pad of an interposer chip.

According to example embodiments, a stacked semiconductor package mayinclude a circuit element in which a wire may have a polarity and maycause a current flow to a bonding pad of an interposer chip. Thus,non-stick defects, e.g., a bonding wire that is not properly bondedduring wire-bonding, may be detected.

Accordingly, cases in which all semiconductor chips in a stackedsemiconductor package are determined to be defective may be reduced orprevented, thereby increasing yield and reducing the burden of testingin subsequent processes.

While the example embodiments have been particularly shown anddescribed, it will be understood by those of ordinary skill in the artthat various changes in form and details may be made therein withoutdeparting from the spirit and scope of the present invention.

1. A stacked semiconductor package comprising: a wiring substrate; afirst semiconductor chip disposed on the wiring substrate andwire-bonded to the wiring substrate; an interposer chip disposed on thefirst semiconductor chip and wire-bonded to the wiring substrate, theinterposer chip including a diode and a bonding pad being electricallyconnected; and a second semiconductor chip disposed on the interposerchip and wire-bonded to the interposer chip, the second semiconductorchip being electrically connected to the wiring substrate through theinterposer chip, wherein the diode is connected to a grounding pad or agrounding line of the interposer chip and the diode includes, a P wellformed below the bonding pad and the grounding pad in the interposerchip, the P well being electrically connected to the grounding pad, andan N+ well formed below the bonding pad in the P well, the N+ well beingelectrically connected to the bonding pad.
 2. The stacked semiconductorpackage of claim 1, wherein the circuit element is connected to agrounding pad or a grounding line of the interposer chip.
 3. The stackedsemiconductor package of claim 1, wherein a resistance of the diode isless than about 8 MOhm.
 4. The stacked semiconductor package of claim 1,wherein the first semiconductor chip, interposer, and secondsemiconductor chip are stacked horizontally on the wiring substrate. 5.The stacked semiconductor package of claim 1, wherein the firstsemiconductor chip, interposer, and second semiconductor chip arestacked vertically on the wiring substrate.
 6. The stacked semiconductorpackage of claim 1, further comprising: a third semiconductor chip onthe second semiconductor chip and wire-bonded to the interposer chip. 7.A stacked semiconductor package, comprising: a wiring substrate; a firstsemiconductor chip disposed on the wiring substrate and wire-bonded tothe wiring substrate; an interposer chip disposed on the firstsemiconductor chip and wire-bonded to the wiring substrate, theinterposer chip including a capacitor and a bonding pad beingelectrically connected; and a second semiconductor chip disposed on theinterposer chip and wire-bonded to the interposer chip, the secondsemiconductor chip being electrically connected to the wiring substratethrough the interposer chip, wherein the capacitor is connected to agrounding pad or a grounding line of the interposer chip, and acapacitance of the capacitor is about 15 to 20 pF.
 8. The stackedsemiconductor package of claim 7, further comprising: a thirdsemiconductor chip on the second semiconductor chip and wire-bonded tothe interposer chip.